Revision as of 15:54, 26 March 2016

Objective

In this tutorial we are going to discuss the TImer module of LPC1768.
First we will see how to configure the Timer0 and Timer1 registers to generate delay of 100ms and 500ms respectively. At the end we will see how to use the ExploreEmdedded Timer library.

LPC1768 Timer Module

LPC1768 has four 32-bit independent timers (Timer0-Timer3). Each timer has a 32-bit pre-scalar to generate wide range on delays. Each timer has 4 match registers with which 4 different delays can be generated using a single timer. Below table shows the registers associated with timers.

Adc Channel	Port Pin	Pin Functions	Associated PINSEL Register	Corresponding Match Register
PWM_1	P2.0	0-GPIO, 1-PWM1[1], 2-TXD1, 3-	0,1 bits of PINSEL4	MR1
PWM_2	P2.1	0-GPIO, 1-PWM1[2], 2-RXD1, 3-	2,3 bits of PINSEL4	MR2
PWM_3	P2.2	0-GPIO, 1-PWM1[3], 2-CTS1, 3-TRACEDATA[3]	4,5 bits of PINSEL4	MR3
PWM_4	P2.3	0-GPIO, 1-PWM1[4], 2-DCD1, 3-TRACEDATA[2]	6,7 bits of PINSEL4	MR4
PWM_5	P2.4	0-GPIO, 1-PWM1[5], 2-DSR1, 3-TRACEDATA[1]	8,9 bits of PINSEL4	MR5
PWM_6	P2.5	0-GPIO, 1-PWM1[6], 2-DTR1, 3-TRACEDATA[0]	10,11 bits of PINSEL4	MR6

LPC7168 Timer Registers

The below table shows the registers associated with LPC1768 Timer module.

Register	Description
IR	Interrupt Register: The IR can be read to identify which of 6(4-match, 2-Capture) possible interrupt sources are pending. Writing Logic-1 will clear the corresponding interrupt.
TCR	Timer Control Register: The TCR is used to control the Timer Counter functions(enable/disable/reset).
TC	Timer Counter: The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
PR	Prescalar Register: This is used to specify the Prescalar value for incrementing the TC.
PC	Prescale Counter: The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented.
MCR	Match Control Register: The MCR is used to control the reseting of TC and generating of interrupt whenever a Match occurs.
MR0-MR3	Match Registers: The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register.

Register Configuration

TCR
31:2	1	0
Reserved	Counter Reset	Counter Enable

Bit 0 – Counter Enable
This bit is used to Enable or Disable the PWM Timer and PWM Prescalar Counters
0- Disable the Counters
1- Enable the Counter incrementing.

Bit 1 – Counter reset
This bit is used to clear the PWM Timer and PWM Prescalar Counter values.
0- Do not Clear.
1- The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK.

MCR
31:21	11	10	9	8	7	6	5	4	3	2	1	0
Reserved	MR3S	MR3R	MR3I	MR2S	MR2R	MR2I	MR1S	MR1R	MR1I	MR0S	MR0R	MR0I

MRxI
This bit is used to Enable or Disable the Timer interrupts when the TC matches MRx (x:0-3)
0- Disable the Timer Match interrupt
1- Enable the Timer Match interrupt.

MRxR
This bit is used to Reset TC whenever it Matches MRx(x:0-3)
0- Do not Clear.
1- Reset TC counter value whenever it matches MRx.

MRxS
This bit is used to Stop TC and PC whenever the TC matches MRx(x:0-3).
0- Disable the Timer stop on match feature
1- Enable the Timer Stop feature. This will stop the Timer whenever the TC reaches the Match register value.

PWM Working

After looking into the PWM registers, its time to see how the LPC1768 PWM module works.

The TC is continuously incremented and once it matches the MR1(Duty Cycle) the PWM pin is pulled Low. TC still continues to increment and once it reaches the Cycle time(Ton+Toff) the PWM module does the following things:

Reset the TC value.
Pull the PWM pin High.
Loads the new Match register values.

Summary of PWM operations for the above image:

Slide1: The TC is being incremented as per the Pre-scalar configuration. The PWM output is high as the TC is still less that duty cycle.
Slide2: TC is incremented to 40 and still the PWM pin as HIGH.
Slide3: TC is incremented to 60 and it matches the Duty Cycle(MR1=60).
Slide4: Now the Comparator1(Green) will trigger the R of SR latch and Pulls the PWM output to Zero(Q=0). TC still continues to increment.
Slide5: TC is incremented to 80 and PWM pin is low as TC>Duty Cycle.
Slide6: Now TC is 100 and it matches the Cycle time(MR0==100).
Slide7: Now the Comparator2(Red) will trigger the S of SR latch and pulls the PWM output to ONE(Q==1). It also resets the TC to zero. It updates Shadow buffers with new Match values from MRO,MR1.

Steps to Configure PWM

Configure the GPIO pins for PWM operation in respective PINSEL register.
Configure TCR to enable the Counter for incrementing the TC, and Enable the PWM block.
Set the required pre-scalar value in PR. In our case it will be zero.
Configure MCR to reset the TC whenever it matches MR0.
Update the Cycle time in MR0. In our case it will be 100.
Load the Duty cycles for required PWMx channels in respective match registers MRx(x: 1-6).
Enable the bits in LER register to load and latch the new match values.
Enable the required pwm channels in PCR register.

Example

Program to demonstrates the variable PWM signal generation on PWM_1-PWM_4(P2_0 - P2_3).
Connect the Leds to the pins P2_0 to P2_3 and observe the led brigthness change depending on the dutycycle.

Using ExploreEmbedded Libraries :

In the above tutorial we just discussed how to configure and use the PWM module of LPC1768
Once you know the internals of LPC7168 PWM, you can directly use the ExploreEmbedded libraries to generate the required PWM signals for different duty cycles.
The below sample code shows how to use the ExploreEmbedded PWM library.

Downloads

Download the complete project folder from the below link: https://codeload.github.com/ExploreEmbedded/Explore-Cortex-M3-LPC1768-Stick-DVB-14001/zip/master

Have a opinion, suggestion , question or feedback about the article let it out here!

@@ Line 49: / Line 49: @@
 =Register Configuration=
-The below table shows the registers associated with LPC1768 PWM.<br>
 {| class="table table-striped table-hover table-condensed table-bordered"
 |-class="info"
 !TCR
 |-
-|31:4|| 3 || 2|| 1 || 0
+|31:2|| 1 || 0
 |-class="active"
-|Reserved|| PWM Enable || Reserved || Counter Reset || Counter Enable
+|Reserved||  Counter Reset || Counter Enable
 |}
@@ Line 68: / Line 67: @@
 - Do not Clear.<br>
 - The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK.
-'''Bit 3 – PWM Enable'''<br>
-Used to Enable or Disable the PWM Block.<br>
-- PWM Disabled<br>
-- PWM Enabled
 <br><br><br>
@@ Line 80: / Line 74: @@
 !MCR
 |-
-|31:21||20||19||18||-||5||4||3||2||1||0
+|31:21||11||10||9||8||7||6||5||4||3||2||1||0
 |-class="active"
-|Reserved||PWMMR6S||PWMMR6R||PWMMR6I||-||PWMMR1S||PWMMR1R||PWMMR1I||PWMMR0S||PWMMR0R||PWMMR0I
+|Reserved||MR3S||MR3R||MR3I||MR2S||MR2R||MR2I||MR1S||MR1R||MR1I||MR0S||MR0R||MR0I
 |}
-'''PWMMRxI'''<br>
+'''MRxI'''<br>
-This bit is used to Enable or Disable the PWM interrupts when the PWMTC matches PWMMRx (x:0-6)<br>
+This bit is used to Enable or Disable the Timer interrupts when the TC matches MRx (x:0-3)<br>
-- Disable the PWM Match interrupt<br>
+- Disable the Timer Match interrupt<br>
-- Enable the PWM Match interrupt.
+- Enable the Timer Match interrupt.
-'''PWMMRxR'''<br>
+'''MRxR'''<br>
-This bit is used to Reset PWMTC whenever it Matches PWMRx(x:0-6)<br>
+This bit is used to Reset TC whenever it Matches MRx(x:0-3)<br>
 - Do not Clear.<br>
-- Reset the PWMTC counter value whenever it matches PWMRx.
+- Reset TC counter value whenever it matches MRx.
-'''PWMMRxS'''<br>
+'''MRxS'''<br>
-This bit is used to Stop the PWMTC,PWMPC whenever the PWMTC matches PWMMRx(x:0-6).<br>
+This bit is used to Stop TC and PC whenever the TC matches MRx(x:0-3).<br>
-- Disable the PWM stop o match feature<br>
+- Disable the Timer stop on match feature<br>
-- Enable the PWM Stop feature. This will stop the PWM whenever the PWMTC reaches the Match register value.
+- Enable the Timer Stop feature. This will stop the Timer whenever the TC reaches the Match register value.
 <br><br><br>
-{| class="table table-striped table-hover table-condensed table-bordered"
-|-class="info"
-!PCR
-|-
-|31:15||      14-9    ||   8-7  ||         6-2         ||1-0
-|-class="active"
-|Unused||PWMENA6-PWMENA1||Unused||PWMSEL6-PWMSEL2||Unused
-|}
-'''PWMSELx'''<br>
-This bit is used to select the single edged and double edge mode form PWMx (x:2-6)<br>
-- Single Edge mode for PWMx<br>
-- Double Edge Mode for PWMx.
-'''PWMENAx'''<br>
-This bit is used to enable/disable the PWM output for PWMx(x:1-6)<br>
-- PWMx Disable.<br>
-- PWMx Enabled.
-<br><br><br>
-{| class="table table-striped table-hover table-condensed table-bordered"
-|-class="info"
-!LER
-|-
-|31-7||6||5||4||3||2||1||0
-|-class="active"
-|Unused||LEN6||LEN5||LEN4||LEN3||LEN2||LEN1||LEN0
-|}
-'''LENx'''<br>
-This bit is used Enable/Disable the loading of new Match value whenever the PWMTC is reset(x:0-6)<br>
-PWMTC will be continously incrementing whenever it reaches the PWMMRO, timer will be reset depeding on PWMTCR configuraion.
-Once the Timer is reset the New Match values will be loaded from MR0-MR6 depending on bits set in this register.<br>
-- Disable the loading of new Match Values<br>
-- Load the new Match values from MRx when the timer is reset.
-<br><br><br><br><br>
 =PWM Working=

Difference between revisions of "LPC1768: Timers"