Revision as of 22:22, 23 May 2015

Objective

In this tutorial we are going to discuss how to use the inbuilt LPC1768 ADC.
Here we will discuss the register associated with ADC and mainly we will focus on basic registers required for ADC.
The other features like Burst Conversion, accessing different register for each channel, ADC conversion depending on Timers,ADC Interrupts etc will be out of scope of this tutorial.
Later we will see how to interface a POT,LDR,Temp Sensor(LM35).
Finally we will see how to use the ExploreEmbedded libraries for ADC.

LPC1768 ADC Block

LPC1768 has an inbuilt 12 bit Successive Approximation ADC which is multiplexed among 8 input pins.
The ADC reference voltage is measured across VREFN to VREFP, meaning it can do the conversion within this range. Usually the VREFP is connected to VDD and VREFN is connected to GND.
As LPC1768 works on 3.3 volts, this will be the ADC reference voltage.
Now the resolution of ADC = 3.3/(2^12) = 3.3/4096 =0.000805 = 0.8mV

ADC pins

The below block diagram shows the ADC input pins multiplexed with other GPIO pins.
The ADC pin can be enabled by configuring the corresponding PINSEL register to select ADC function.

ADC Registers

The below table shows the registers associated with LPC1768 ADC.
We are going to focus only on ADCR and ADGDR as these are sufficient for simple A/D conversion.
However once you are familer with LPC1768 ADC, you can explore the other features and the associated registers.

ADC Register Configuration

Now lets see how to configure the individual registers for ADC conversion.

ADCR ( ADC Control Register )

This registers contains the bits for channel selection, ADC conversion clock speed and Starting the conversion.

Bit 7:0 – SEL : Channel Select

These bits select which of the AD0.7:0 pins is (are) to be sampled and converted. There is one bit per channel e. g. bit o for AD0, bit 7 AD7.

Digital signals are disconnected from the ADC input pins when the ADC function is selected on that pin in the Pin Select register

Write one to enable respective channel. All zeroes is equivalent to 0x01.

Bit 15:8 – CLCKDIV : Clock Divisor

The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 13 MHz.

Bit 16 – BURST

Repeated conversions can be terminated by clearing this bit.

Bit 21 – PDN : Power Down Mode

Setting this bit brings ADC out of power down mode and makes it operational.

Bit 24:26 – START

When the BURST bit is 0, these bits control whether and when an A/D conversion is started:

The remaining cases (010 to 111) are about starting conversion on occurrence of edge on a particular CAP or MAT pin.

Bit 27 - EDGE

This bit is significant only when the START field contains 010-111. It starts conversion on selected CAP or MAT input.

ADGDR ( ADC Global Data Register )

Bit 15:4 - RESULT

When DONE is 1, this field contains a digital value equivalent to the voltage on the AD0[n] pin selected by the SEL field in ADCR register.

Bit 23:16 - CHN : Channel

These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 011 channel 3...).

Bit 27 - OVERRUN

This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.

Bit 31 - DONE

This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.

Some other registers

Though there are some more registers, we are restricting ourselves to use these registers only as this will be more convenient.

Apart from ADC Global Data register there are more 8 ADC Data registers (one Data register per ADC channel). DONE and OVERRUN bits for each channel can be monitored separately from the bits present in ADC Status register.

One can use the A/D Global Data Register to read all data from the ADC else use the A/D Channel Data Registers. It is important to use one method consistently because the DONE and OVERRUN flags can otherwise get out of synch between the AD0GDR and the A/D Channel Data Registers, potentially causing erroneous interrupts or DMA activity.

Schematic

Code

/*-----------------------------------------------------------------------------
note : Refer adc.h to enable ADC channels.
------------------------------------------------------------------------------*/
#include "lpc17xx.h"	//device specific heaader file
#include "uart.h"		//Explore Embedded UART library which conatins the lcd routines
#include "adc.h"		//Explore Embedded ADC library which conatins the adc routines
 
/* start the main program */
int main() 
{
   uint16_t adc_result;
 
  /* Setup and initialize the microcontroller system */
	SystemInit();
 
  /* Initialize the UART before displaying any thing on the lcd */
	UART_Init(UART0,9600);
 
  /* Initialize the adc before starting the conversion */
	ADC_Init();
 
  /* Display "ADC Channel zero" on first line*/
	UART_Printf("ADC Channel five");
 
   /* Display the adc channel zero value continously */ 
   while(1)
    {
		/*Get the adc value of channel five */
		adc_result= ADC_GetAdcValue(5);
 
		/*Display the adc value on UART*/
		UART_Printf("\n %u",adc_result);
	}
}