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| − | [[category: ARM Tutorials]] | + | #REDIRECT [[LPC1768: UART Programming]] |
| − | [[User:Amruta|Amruta]] ([[User talk:Amruta|talk]]) 13:22, 17 March 2015 (IST)
| + | |
| − | ----
| + | |
| − | =Basics=
| + | |
| − | | + | |
| − | LPC1768 has 4 UARTS out of which UART0, UART2, UART3 are very similar while UART1 is little bit different from all these. | + | |
| − | | + | |
| − | ===Registers===
| + | |
| − | Let's have a brief review of some of the important UART registers.
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| − | | + | |
| − | ====RBR ( Receiver Buffer Register )====
| + | |
| − | The RBR is the top byte of the UART receiver FIFO. The top byte of this FIFO contains
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| − | the oldest character received.
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| − | | + | |
| − | The data byte is available in the register bits 0:7.
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| − | | + | |
| − | While accessing this register, the DLAB bit in LCR must be zero.
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| − | | + | |
| − | ====THR ( Transmit Holding Register )====
| + | |
| − | The THR is the top byte of the UART transmitter FIFO. The top byte is the newest character in
| + | |
| − | the this FIFO.
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| − | | + | |
| − | The data byte to be transmitted is written in the register bits 0:7.
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| − | | + | |
| − | While accessing this register, the DLAB bit in LCR must be zero.
| + | |
| − | | + | |
| − | ====DLL ( Divisor Latch LSB register ) and DLM ( Divisor Latch MSB register )====
| + | |
| − | The DLL and DLM registers together form a 16-bit divisor where DLL contains the lower 8 bits of the
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| − | divisor and DLM contains the higher 8 bits of the divisor.
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| − | | + | |
| − | This holds the value used for UART baud rate generation.
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| − | | + | |
| − | While accessing this any of these registers, the DLAB bit in LCR must be one.
| + | |
| − | | + | |
| − | ====FCR ( FIFO Control Register )====
| + | |
| − | This register controls the operation of the UART Rx and TX FIFOs.
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| − | | + | |
| − | {| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
| + | |
| − | !colspan = '8'|FCR
| + | |
| − | |-
| + | |
| − | |31:8||7:6 ||5:4||3|| 2 || 1 || 0
| + | |
| − | |-
| + | |
| − | | Reserved ||Rx Trigger Level|| Reserved ||DMA Mode Select||Tx FIFO Reset||Rx FIFO Reset||FIFO Enable
| + | |
| − | |}
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| − | | + | |
| − | '''Bit 0 - : FIFO Enable'''
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| − | | + | |
| − | Write 1 enable both Tx and Rx FIFOs of UART and 0 to disable them.
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| − | | + | |
| − | This bit must be set for proper UART operation.
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| − | | + | |
| − | '''Bit 1 - : Rx FIFO Reset'''
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| − | | + | |
| − | Writing 0 has no impact on either of FIFOs.
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| − | | + | |
| − | Writing a logic 1 will clear all bytes in UART receiver FIFO, reset the pointer logic.
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| − | | + | |
| − | This bit is self-clearing.
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| − | | + | |
| − | '''Bit 2 - : Tx FIFO Reset'''
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| − | | + | |
| − | Writing 0 has no impact on either of FIFOs.
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| − | | + | |
| − | Writing a logic 1 will clear all bytes in UART transmitter FIFO, reset the pointer logic.
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| − | | + | |
| − | This bit is self-clearing.
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| − | | + | |
| − | '''Bit 3 - : DMA Mode Select'''
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| − | | + | |
| − | When the FCR[0] is set, this bit selects the DMA mode
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| − | | + | |
| − | '''Bit 7:6 - : Rx Trigger Level'''
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| − | | + | |
| − | These two bits determine how many receiver UARTn FIFO characters must be
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| − | written before an interrupt or DMA request is activated
| + | |
| − | {| class="wikitable" style="text-align:center; background-color:#C0C0C0;;"
| + | |
| − | !Bit Value || Trigger Level || Characters
| + | |
| − | |-
| + | |
| − | |00|| 0||1
| + | |
| − | |-
| + | |
| − | |01|| 1||4
| + | |
| − | |-
| + | |
| − | |10|| 2||8
| + | |
| − | |-
| + | |
| − | |11|| 3||14
| + | |
| − | |-
| + | |
| − | |}
| + | |
| − | | + | |
| − | ====LCR ( Line Control Register )====
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| − | {| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
| + | |
| − | !colspan = '8'|LCR
| + | |
| − | |-
| + | |
| − | |31:8||7||6 ||5:4||3|| 2 || 1 : 0
| + | |
| − | |-
| + | |
| − | | Reserved||DLAB||Break Control||Parity Select||Parity Enable||Stop Bit||Word Length
| + | |
| − | |}
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| − | | + | |
| − | '''Bit 1:0 - Word Length Select '''
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| − | {| class="wikitable" style="text-align:center; background-color:#C0C0C0;;"
| + | |
| − | !Value || Character Length
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| − | |-
| + | |
| − | |00|| 5 bit
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| − | |-
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| − | |01|| 6 bit
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| − | |-
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| − | |10|| 7 bit
| + | |
| − | |-
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| − | |11|| 8 bit
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| − | |-
| + | |
| − | |}
| + | |
| − | '''Bit 2 - Stop Bit Select '''
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| − | | + | |
| − | Writing 0 select 1 stop bit while writing 0 selects 2 stop bits
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| − | | + | |
| − | '''Bit 3 - Parity Enable'''
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| − | | + | |
| − | Write 1 to enable parity generation and 0 to disable it.
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| − | | + | |
| − | '''Bit 5:4 - Parity Select'''
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| − | {| class="wikitable" style="text-align:center; background-color:#C0C0C0;"
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| − | !Value || Parity
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| − | |-
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| − | |00|| Odd Parity
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| − | |-
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| − | |01|| Even Parity
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| − | |-
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| − | |10|| Forced '1' sticky parity
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| − | |-
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| − | |11|| Forced '0' sticky parity
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| − | |-
| + | |
| − | |}
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| − | | + | |
| − | | + | |
| − | '''Bit 6 - Break Control'''
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| − | | + | |
| − | Write 1 to enable break transmission and 0 to disable it.
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| − | | + | |
| − | '''Bit 7 - DLAB : Divisor Latch Bit'''
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| − | | + | |
| − | Write 1 to enable access to Divisor Latches and 0 to disable the access.
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| − | | + | |
| − | ====LSR ( Line Status Register )====
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| − | {| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
| + | |
| − | !colspan = '9'|LSR
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| − | |-
| + | |
| − | |31:8|| 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
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| − | |-
| + | |
| − | |Reserved||RXFE||TEMT||THRE|| BI || FE || PE || OV || RDR
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| − | |}
| + | |
| − | '''Bit 0 - RDR : Receiver Data Ready'''
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| − | | + | |
| − | It gives the status of UART Rx FIFO.
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| − | {| class="wikitable" style="text-align:center; background-color:#C0C0C0;"
| + | |
| − | !Bit Value || FIFO Status
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| − | |-
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| − | |0|| Empty
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| − | |-
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| − | |1|| Not Empty
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| − | |-
| + | |
| − | |}
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| − | | + | |
| − | '''Bit 1 - OV : Overrun Error'''
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| − | '''Bit 2 - PE : Parity Error'''
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| − | '''Bit 3 - FE : Framing Error'''
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| − | '''Bit 4 - BI : Break Interrupt'''
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| − | All of above bits gives respective status.
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| − | | + | |
| − | {| class="wikitable" style="text-align:center; background-color:#C0C0C0;"
| + | |
| − | !Bit Value || Status
| + | |
| − | |-
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| − | |0|| Inactive
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| − | |-
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| − | |1|| Active
| + | |
| − | |-
| + | |
| − | |}
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| − | | + | |
| − | '''Bit 5 - THRE : Transmitter Holding Register Empty'''
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| − | | + | |
| − | It is set immediately upon detection of an empty THR and is cleared on a THR write.
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| − | | + | |
| − | '''Bit 6 - TEMT : Transmitter Empty'''
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| − | It is set when both THR and TSR are empty and is cleared when
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| − | either the TSR or the THR contain valid data.
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| − | | + | |
| − | '''Bit 7 - RXFE : Error in RX FIFO '''
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| − | | + | |
| − | It is set when UART RBR contains at least one UART RX error and is cleared if RBR contains no UART RX errors or UFCR[0]=0.
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| − | | + | |
| − | ===Baud-rate Calculations===
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| − | | + | |
| − | =Schematic=
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| − | [[File:Schematic LPC1768 UART.svg|x500px|center|Schematic]]
| + | |
| − | | + | |
| − | =Code=
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| − | | + | |
| − | Let's make a Decimal Counter with UART .
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| − | | + | |
| − | Initialize the UART0 with 9600 baud-rate.
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| − | | + | |
| − | Display the initial message and go on displaying incremented count taking some pause.
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| − | | + | |
| − | To know more about UART library, [[UART|check this]].
| + | |
| − | <syntaxhighlight>
| + | |
| − | #include "lpc17xx.h" //Device specific header file
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| − | #include "uart.h" //Explore Embedded UART library which contains the uart routines
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| − | #include "delay.h" //Explore Embedded library containing the delay routines
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| − | | + | |
| − | /* start the main program */
| + | |
| − | int main()
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| − | {
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| − | uint16_t cnt=0;
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| − |
| + | |
| − | /* Setup and initialize the microcontroller system */
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| − | SystemInit();
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| − | | + | |
| − | /* Initialize the UART before Transmitting/Receiving any data */
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| − | UART_Init(UART0,9600);
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| − | | + | |
| − | UART_Printf("5digit decimal counter: ");
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| − | | + | |
| − | /* Transmit the counter till 9999 */
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| − | while(cnt < 9999)
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| − | {
| + | |
| − | /* Transmit the 4-digit counter value and go to next line */
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| − | UART_Printf("\n\r%4u",cnt);
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| − |
| + | |
| − | /* Increment the counter value after 1-sec */
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| − | DELAY_sec(1);
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| − | cnt++;
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| − | }
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| − | while(1);
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| − | }
| + | |
| − | </syntaxhighlight>
| + | |
| − | {{DISQUS}}
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