Line 58: Line 58:
 
|-
 
|-
 
|31:8|| 7 || 6 || 5 ||  4  || 3 || 2 || 1 || 0   
 
|31:8|| 7 || 6 || 5 ||  4  || 3 || 2 || 1 || 0   
 +
|-
 +
|Reserved||RXFE||TEMT||THRE||  BI  || FE || PE || OV || RDR
 +
|}
 +
 +
"Bit 0 - RDR : Receiver Data Ready"
 +
It gives the status of UART Rx FIFO.
 +
{| class="wikitable" style="text-align:center; background-color:#ABCCEF;"
 +
!Bit Value || FIFO Status
 +
|-
 +
|0|| Empty
 +
|1|| Not Empty
 
|-
 
|-
 
|Reserved||RXFE||TEMT||THRE||  BI  || FE || PE || OV || RDR
 
|Reserved||RXFE||TEMT||THRE||  BI  || FE || PE || OV || RDR

Revision as of 17:11, 17 March 2015

Amruta (talk) 13:22, 17 March 2015 (IST)


Basics

LPC1768 has 4 UARTS out of which UART0, UART2, UART3 are very similar while UART1 is little bit different from all these.

Registers

Let's have a brief review through some of the important UART registers.

RBR ( Receiver Buffer Register )

The RBR is the top byte of the UART receiver FIFO. The top byte of this FIFO contains the oldest character received.

The data byte is available in the register bits 0:7.

While accessing this register, the DLAB bit in LCR must be zero.

THR ( Transmit Holding Register )

The THR is the top byte of the UART transmitter FIFO. The top byte is the newest character in the this FIFO.

The data byte to be transmitted is written in the register bits 0:7.

While accessing this register, the DLAB bit in LCR must be zero.

DLL ( Divisor Latch LSB register ) and DLM ( Divisor Latch MSB register )

The DLL and DLM registers together form a 16-bit divisor where DLL contains the lower 8 bits of the divisor and DLM contains the higher 8 bits of the divisor.

This holds the value used for UART baud rate generation.

While accessing this any of these registers, the DLAB bit in LCR must be one.

FCR ( FIFO Control Register )

This register controls the operation of the UART Rx and TX FIFOs.

FCR
31:8 7:6 5:4 3 2 1 0
Reserved Rx Trigger Level Reserved DMA Mode Select Tx FIFO Reset Rx FIFO Reset FIFO Enable

LCR ( Line Control Register )

LCR
31:8 7 6 5:4 3 2 1 : 0
Reserved DLAB Break Control Parity Select Parity Enable Stop Bit Word Length

LSR ( Line Status Register )

LSR
31:8 7 6 5 4 3 2 1 0
Reserved RXFE TEMT THRE BI FE PE OV RDR

"Bit 0 - RDR : Receiver Data Ready" It gives the status of UART Rx FIFO.

Bit Value FIFO Status
0 Empty 1 Not Empty
Reserved RXFE TEMT THRE BI FE PE OV RDR

Schematic

Code

Let's make a Decimal Counter with UART .

Initialize the UART0 with 9600 baud-rate.

Display the initial message and go on displaying incremented count taking some pause.

To know more about UART library, check this.

#include "lpc17xx.h" //Device specific header file
#include "uart.h"	//Explore Embedded UART library which contains the uart routines
#include "delay.h" //Explore Embedded  library containing the delay routines
 
/* start the main program */
int main()
{
	uint16_t cnt=0;
 
        /* Setup and initialize the microcontroller system */
	SystemInit();
 
	/* Initialize the UART before Transmitting/Receiving any data */
	UART_Init(UART0,9600);
 
	UART_Printf("5digit decimal counter: ");
 
	/* Transmit the counter till 9999 */
	while(cnt < 9999)
	{
		/* Transmit the 4-digit counter value and go to next line */
		UART_Printf("\n\r%4u",cnt);
 
		/* Increment the counter value after 1-sec */
		DELAY_sec(1);
		cnt++;
	}
	while(1);
}