Difference between revisions of "ARM ADC Programming"
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Here we will discuss commonly used ADC registers. | Here we will discuss commonly used ADC registers. | ||
=====ADCR ( ADC Control Register )===== | =====ADCR ( ADC Control Register )===== | ||
+ | |||
{| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto" | {| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto" | ||
!colspan = '9'|ADCR | !colspan = '9'|ADCR | ||
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|Reserved||EDGE||START||Reserved|| PDN || Reserved || BURST || CLCKDIV || SEL | |Reserved||EDGE||START||Reserved|| PDN || Reserved || BURST || CLCKDIV || SEL | ||
|} | |} | ||
+ | |||
+ | '''Bit 7:0 – SEL : Channel Select''' | ||
+ | These bits select which of the AD0.7:0 pins is (are) to be sampled and converted. There is one bit per channel e. g. bit o for AD0, bit 7 AD7. | ||
+ | Write one to enable respective channel. | ||
+ | All zeroes is equivalent to 0x01. | ||
+ | '''Bit 15:8 – CLCKDIV : Clock Divisor''' | ||
+ | The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 13 MHz. | ||
+ | '''Bit 16 – BURST''' | ||
+ | Repeated conversions can be terminated by clearing this bit. | ||
+ | '''Bit 21 – PDN : Power Down Mode''' | ||
+ | Setting this bit brings ADC out of power down mode and makes it operational. | ||
+ | '''Bit 24:26 – START''' | ||
+ | When the BURST bit is 0, these bits control whether and when an A/D conversion is started: | ||
=====ADGDR ( ADC Global Data Register )===== | =====ADGDR ( ADC Global Data Register )===== |
Revision as of 13:44, 18 March 2015
Amruta (talk) 13:28, 17 March 2015 (IST)
Contents
Basics
LPC1768 has 12 bit ADC which is multiplexed among 8 input pins. It's measurement range is typically 3V which means that ADC resolution is approximately 0.7 mV.
Registers
Here we will discuss commonly used ADC registers.
ADCR ( ADC Control Register )
ADCR | ||||||||
---|---|---|---|---|---|---|---|---|
31:28 | 27 | 26:24 | 23:22 | 21 | 20:17 | 16 | 15:8 | 7:0 |
Reserved | EDGE | START | Reserved | PDN | Reserved | BURST | CLCKDIV | SEL |
Bit 7:0 – SEL : Channel Select These bits select which of the AD0.7:0 pins is (are) to be sampled and converted. There is one bit per channel e. g. bit o for AD0, bit 7 AD7. Write one to enable respective channel. All zeroes is equivalent to 0x01. Bit 15:8 – CLCKDIV : Clock Divisor The APB clock (PCLK_ADC0) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 13 MHz. Bit 16 – BURST Repeated conversions can be terminated by clearing this bit. Bit 21 – PDN : Power Down Mode Setting this bit brings ADC out of power down mode and makes it operational. Bit 24:26 – START When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
ADGDR ( ADC Global Data Register )
ADCR | ||||||||
---|---|---|---|---|---|---|---|---|
31 | 27 | 26:24 | 23:16 | 15:4 | 3:0 | |||
Done | EDGE | Channel | Reserved | RESULT | Reserved |
Schematic
Code
/*----------------------------------------------------------------------------- note : Refer adc.h to enable ADC channels. ------------------------------------------------------------------------------*/ #include "lpc17xx.h" //device specific heaader file #include "uart.h" //Explore Embedded UART library which conatins the lcd routines #include "adc.h" //Explore Embedded ADC library which conatins the adc routines /* start the main program */ int main() { uint16_t adc_result; /* Setup and initialize the microcontroller system */ SystemInit(); /* Initialize the UART before displaying any thing on the lcd */ UART_Init(UART0,9600); /* Initialize the adc before starting the conversion */ ADC_Init(); /* Display "ADC Channel zero" on first line*/ UART_Printf("ADC Channel zero"); /* Display the adc channel zero value continously */ while(1) { /*Get the adc value of channel five */ adc_result= ADC_GetAdcValue(5); /*Display the adc value on UART*/ UART_Printf("\n %u",adc_result); } }