Difference between revisions of "ALU in Detail"

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{{box|type=l_green_light|text= You should have heard of an Arithmetic and Logic Unit before, while discussing a Computer CPU or a micro controller. In this tutorial we will look at what an ALU really is? <br />
 
{{box|type=l_green_light|text= You should have heard of an Arithmetic and Logic Unit before, while discussing a Computer CPU or a micro controller. In this tutorial we will look at what an ALU really is? <br />
 
We will discuss a 4 bit ALU; this would limit many possibilities 16. We would assume that associated registers and instruction set are also 4 bit.<br />
 
We will discuss a 4 bit ALU; this would limit many possibilities 16. We would assume that associated registers and instruction set are also 4 bit.<br />
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=== Half Adder ===
  
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'''half adder''' adds two single binary digits ''A'' and ''B''. It has two outputs, sum (''S'') and carry (''C''). The carry signal represents an overflow into the next digit of a multi-digit addition.Figures below illustrate a simple half adder constructed from logic gates
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=== The basic Unit: 1 bit ALU===
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[[File:1bitALU.jpg|400x350px|framed]]
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We assume you are familiar with logic gates, and also have come across a 1 bit adder. It simple adds two 1 bit inputs as shown below.
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{| class="wikitable" style="text-align:center"
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[[File:HalfAdder.png|right|thumb|Half adder logic diagram]]
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{| class="wikitable" style="text-align:left"
 
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!colspan="2"| Inputs !!colspan="2"| Outputs
 
!colspan="2"| Inputs !!colspan="2"| Outputs
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| 1 || 1 || 0  || 1
 
| 1 || 1 || 0  || 1
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=== Full Adder===
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{{box|type=l_green_light|text=
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''Full Adder'' is an extension of half adder to include the Cin input as well. The truth table can be implemented to form the logic diagram as shown below.
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[[File:FullAdder.jpeg|thumbnail|Full Adder]]
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{| class="wikitable" style="text-align:center"
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|-
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!colspan="3"| Inputs !!colspan="2"| Outputs
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|-
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! ''A'' !! ''B'' !! ''C''<sub>in</sub> !! ''C''<sub>out</sub> !! ''S''
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| 0 || 0 || 0  || 0 || 0
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| 1 || 0 || 0  || 0 || 1
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| 0 || 1 || 0  || 0 || 1
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|-
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| 1 || 1 || 0  || 1 || 0
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|-
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| 0 || 0 || 1  || 0 || 1
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|-
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| 1 || 0 || 1  || 1 || 0
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|-
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| 0 || 1 || 1  || 1 || 0
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|-
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| 1 || 1 || 1  || 1 || 1
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|}
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=== The basic Unit: 1 bit ALU===
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{{box|type=l_green_light|text=
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So with the above building blocks, lets construct a simple ALU that performs a arithmetic operation (1 bit addition)and does 3 logical operations namely AND, NOR and XOR as shown below. The multiplexer selects only one operation at a time.
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The operation selected depends on the selection lines of the multiplexer as shown in the truth table.
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}}
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[[File:1bitALU.jpg|1080x660px|framed]]
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{| class="wikitable" style="text-align:left"
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|-
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!colspan="2"| Inputs !!colspan="2"| Outputs
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|-
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! ''M1'' !! ''M0'' !! ''Operation''
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| 0 || 0 || SUM
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| 1 || 0 || AND
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| 0 || 1 || OR
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| 1 || 1 || XOR
 
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Revision as of 13:03, 8 December 2013

Arithmetic and Logic Unit in Detail

You should have heard of an Arithmetic and Logic Unit before, while discussing a Computer CPU or a micro controller. In this tutorial we will look at what an ALU really is?
We will discuss a 4 bit ALU; this would limit many possibilities 16. We would assume that associated registers and instruction set are also 4 bit.

Half Adder

half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition.Figures below illustrate a simple half adder constructed from logic gates

Half adder logic diagram
Inputs Outputs
A B S C
0 0 0 0
1 0 1 0
0 1 1 0
1 1 0 1

Full Adder

Full Adder is an extension of half adder to include the Cin input as well. The truth table can be implemented to form the logic diagram as shown below.

Full Adder
Inputs Outputs
A B Cin Cout S
0 0 0 0 0
1 0 0 0 1
0 1 0 0 1
1 1 0 1 0
0 0 1 0 1
1 0 1 1 0
0 1 1 1 0
1 1 1 1 1

The basic Unit: 1 bit ALU

So with the above building blocks, lets construct a simple ALU that performs a arithmetic operation (1 bit addition)and does 3 logical operations namely AND, NOR and XOR as shown below. The multiplexer selects only one operation at a time. The operation selected depends on the selection lines of the multiplexer as shown in the truth table.

1bitALU.jpg
Inputs Outputs
M1 M0 Operation
0 0 SUM
1 0 AND
0 1 OR
1 1 XOR
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