In this tutorial we will discuss how to access the PIC16F877A internal EEPROM memory to store and retrieve the data. Eeprom is basically used to store the non volatile data which is required to be stored even if there is power loss or controller resets.
PIC16F877A Memories
PIC16F877A comes with three memories Flash,RAM and EEPROM. Below table shows the memory capacity of PIC16F877A:
| Memory | Size | Description |
|---|---|---|
| FLASH | 8k-bytes | Used to store the programs |
| RAM | 368-bytes | Temporary/ScratchPad memory used during program execution. |
| EEPROM | 256-bytes | Used to store the non-volatile data across power cycles |
EEPROM Registers
The below table shows the registers associated with PIC16F877A UART.
| Register | Description |
|---|---|
| EECON1 | Eeprom read/Write Control register |
| EECON2 | Used to execute special instruction sequence(0x55-0xAA) during write |
| EEDATA | Holds the data to be Written/Read to/from Eeprom. |
| EEADR | Hold the Eeprom memory address from where the data needs to be read/written. |
| EEPCON1 | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EEPGD | - | - | - | WRERR | WREN | WR | RD |
EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not cleared) in software.
0 = Does not initiate an EEPROM read
Steps to Write
- If step 10 is not implemented, check the WR bit to see if a write is in progress.
- Write the address to EEADR. Make sure that the address is not larger than the memory size of the device.
- Write the 8-bit data value to be programmed in the EEDATA register.
- Clear the EEPGD bit to point to EEPROM data memory.
- Set the WREN bit to enable program operations.
- Disable interrupts (if enabled).
- Execute the special five instruction sequence:
- Write 55h to EECON2 in two steps (first to W, then to EECON2)
- Write AAh to EECON2 in two steps (first to W, then to EECON2)
- Set the WR bit
- Enable interrupts (if using interrupts).
- Clear the WREN bit to disable program operations.
- At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set.
- (EEIF must be cleared by firmware.) If step 1 is not implemented, then firmware should check for EEIF to be set, or WR to clear, to indicate the
end of the program cycle.