Difference between revisions of "PIC Internal Eeprom"
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|EEADR|| Hold the Eeprom memory address from where the data needs to be read/written. | |EEADR|| Hold the Eeprom memory address from where the data needs to be read/written. | ||
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{| class="table table-striped table-hover table-condensed table-bordered" | {| class="table table-striped table-hover table-condensed table-bordered" | ||
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<b>EEPGD:</b> Program/Data EEPROM Select bit<br> | <b>EEPGD:</b> Program/Data EEPROM Select bit<br> | ||
| − | 1 = Accesses program memory | + | 1 = Accesses program memory<br> |
0 = Accesses data memory | 0 = Accesses data memory | ||
<b>WRERR:</b> EEPROM Error Flag bit<br> | <b>WRERR:</b> EEPROM Error Flag bit<br> | ||
| − | 1 = A write operation is prematurely terminated | + | 1 = A write operation is prematurely terminated<br> |
0 = The write operation completed | 0 = The write operation completed | ||
<b>WREN:</b> EEPROM Write Enable bit<br> | <b>WREN:</b> EEPROM Write Enable bit<br> | ||
| − | 1 = Allows write cycles | + | 1 = Allows write cycles<br> |
0 = Inhibits write to the EEPROM | 0 = Inhibits write to the EEPROM | ||
<b>WR:</b> Write Control bit<br> | <b>WR:</b> Write Control bit<br> | ||
| − | 1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. | + | 1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.<br> |
0 = Write cycle to the EEPROM is complete | 0 = Write cycle to the EEPROM is complete | ||
<b>RD:</b> Read Control bit<br> | <b>RD:</b> Read Control bit<br> | ||
| − | 1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not cleared) in software. | + | 1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not cleared) in software.<br> |
0 = Does not initiate an EEPROM read | 0 = Does not initiate an EEPROM read | ||
=Register Configuration= | =Register Configuration= | ||
Revision as of 12:19, 18 May 2016
In this tutorial we will discuss how to access the PIC16F877A internal EEPROM memory to store and retrieve the data. Eeprom is basically used to store the non volatile data which is required to be stored even if there is power loss or controller resets.
PIC16F877A Memories
PIC16F877A comes with three memories Flash,RAM and EEPROM. Below table shows the memory capacity of PIC16F877A:
| Memory | Size | Description |
|---|---|---|
| FLASH | 8k-bytes | Used to store the programs |
| RAM | 368-bytes | Temporary/ScratchPad memory used during program execution. |
| EEPROM | 256-bytes | Used to store the non-volatile data across power cycles |
EEPROM Registers
The below table shows the registers associated with PIC16F877A UART.
| Register | Description |
|---|---|
| EECON1 | Eeprom read/Write Control register |
| EECON2 | Used to execute special instruction sequence(0x55-0xAA) during write |
| EEDATA | Holds the data to be Written/Read to/from Eeprom. |
| EEADR | Hold the Eeprom memory address from where the data needs to be read/written. |
| EEPCON1 | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EEPGD | - | - | - | WRERR | WREN | WR | RD |
EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not cleared) in software.
0 = Does not initiate an EEPROM read