Difference between revisions of "ARM Communication Protocol : UART"
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| Reserved ||Rx Trigger Level|| Reserved ||DMA Mode Select||Tx FIFO Reset||Rx FIFO Reset||FIFO Enable | | Reserved ||Rx Trigger Level|| Reserved ||DMA Mode Select||Tx FIFO Reset||Rx FIFO Reset||FIFO Enable | ||
|} | |} | ||
+ | |||
+ | '''Bit 0 - : FIFO Enable''' | ||
+ | Write 1 enable both Tx and Rx FIFOs of UART and 0 to disable them. | ||
+ | |||
+ | This bit must be set for proper UART operation. | ||
+ | |||
+ | '''Bit 1 - : Rx FIFO Reset''' | ||
+ | Writing 0 has no impact on either of FIFOs. | ||
+ | |||
+ | Writing a logic 1 will clear all bytes in UART receiver FIFO, reset the pointer logic. | ||
+ | |||
+ | This bit is self-clearing. | ||
+ | '''Bit 2 - : Tx FIFO Reset''' | ||
+ | Writing 0 has no impact on either of FIFOs. | ||
+ | |||
+ | Writing a logic 1 will clear all bytes in UART transmitter FIFO, reset the pointer logic. | ||
+ | |||
+ | This bit is self-clearing. | ||
+ | '''Bit 3 - : DMA Mode Select''' | ||
+ | When the FCR[0] is set, this bit selects the DMA mode | ||
+ | '''Bit 7:6 - : Rx Trigger Level''' | ||
====LCR ( Line Control Register )==== | ====LCR ( Line Control Register )==== |
Revision as of 17:58, 17 March 2015
Amruta (talk) 13:22, 17 March 2015 (IST)
Contents
Basics
LPC1768 has 4 UARTS out of which UART0, UART2, UART3 are very similar while UART1 is little bit different from all these.
Registers
Let's have a brief review through some of the important UART registers.
RBR ( Receiver Buffer Register )
The RBR is the top byte of the UART receiver FIFO. The top byte of this FIFO contains the oldest character received.
The data byte is available in the register bits 0:7.
While accessing this register, the DLAB bit in LCR must be zero.
THR ( Transmit Holding Register )
The THR is the top byte of the UART transmitter FIFO. The top byte is the newest character in the this FIFO.
The data byte to be transmitted is written in the register bits 0:7.
While accessing this register, the DLAB bit in LCR must be zero.
DLL ( Divisor Latch LSB register ) and DLM ( Divisor Latch MSB register )
The DLL and DLM registers together form a 16-bit divisor where DLL contains the lower 8 bits of the divisor and DLM contains the higher 8 bits of the divisor.
This holds the value used for UART baud rate generation.
While accessing this any of these registers, the DLAB bit in LCR must be one.
FCR ( FIFO Control Register )
This register controls the operation of the UART Rx and TX FIFOs.
FCR | |||||||
---|---|---|---|---|---|---|---|
31:8 | 7:6 | 5:4 | 3 | 2 | 1 | 0 | |
Reserved | Rx Trigger Level | Reserved | DMA Mode Select | Tx FIFO Reset | Rx FIFO Reset | FIFO Enable |
Bit 0 - : FIFO Enable Write 1 enable both Tx and Rx FIFOs of UART and 0 to disable them.
This bit must be set for proper UART operation.
Bit 1 - : Rx FIFO Reset Writing 0 has no impact on either of FIFOs.
Writing a logic 1 will clear all bytes in UART receiver FIFO, reset the pointer logic.
This bit is self-clearing. Bit 2 - : Tx FIFO Reset Writing 0 has no impact on either of FIFOs.
Writing a logic 1 will clear all bytes in UART transmitter FIFO, reset the pointer logic.
This bit is self-clearing. Bit 3 - : DMA Mode Select When the FCR[0] is set, this bit selects the DMA mode Bit 7:6 - : Rx Trigger Level
LCR ( Line Control Register )
LCR | |||||||
---|---|---|---|---|---|---|---|
31:8 | 7 | 6 | 5:4 | 3 | 2 | 1 : 0 | |
Reserved | DLAB | Break Control | Parity Select | Parity Enable | Stop Bit | Word Length |
Bit 1:0 - Word Length Select
Value | Character Length |
---|---|
00 | 5 bit |
01 | 6 bit |
10 | 7 bit |
11 | 8 bit |
Bit 2 - Stop Bit Select
Writing 0 select 1 stop bit while writing 0 selects 2 stop bits
Bit 3 - Parity Enable
Write 1 to enable parity generation and 0 to disable it.
Bit 5:4 - Parity Select
Value | Parity |
---|---|
00 | Odd Parity |
01 | Even Parity |
10 | Forced '1' sticky parity |
11 | Forced '0' sticky parity |
Bit 6 - Break Control
Write 1 to enable break transmission and 0 to disable it.
Bit 7 - DLAB : Divisor Latch Bit
Write 1 to enable access to Divisor Latches and 0 to disable the access.
LSR ( Line Status Register )
LSR | ||||||||
---|---|---|---|---|---|---|---|---|
31:8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | RXFE | TEMT | THRE | BI | FE | PE | OV | RDR |
Bit 0 - RDR : Receiver Data Ready
It gives the status of UART Rx FIFO.
Bit Value | FIFO Status |
---|---|
0 | Empty |
1 | Not Empty |
Bit 1 - OV : Overrun Error
Bit 2 - PE : Parity Error
Bit 3 - FE : Framing Error
Bit 4 - BI : Break Interrupt
All of above bits gives respective status.
Bit Value | Status |
---|---|
0 | Inactive |
1 | Active |
Bit 5 - THRE : Transmitter Holding Register Empty
It is set immediately upon detection of an empty THR and is cleared on a THR write.
Bit 6 - TEMT : Transmitter Empty
It is set when both THR and TSR are empty and is cleared when either the TSR or the THR contain valid data.
Bit 7 - RXFE : Error in RX FIFO
It is set when UART RBR contains at least one UART RX error and is cleared if RBR contains no UART RX errors or UFCR[0]=0.
Schematic
Code
Let's make a Decimal Counter with UART .
Initialize the UART0 with 9600 baud-rate.
Display the initial message and go on displaying incremented count taking some pause.
To know more about UART library, check this.
#include "lpc17xx.h" //Device specific header file #include "uart.h" //Explore Embedded UART library which contains the uart routines #include "delay.h" //Explore Embedded library containing the delay routines /* start the main program */ int main() { uint16_t cnt=0; /* Setup and initialize the microcontroller system */ SystemInit(); /* Initialize the UART before Transmitting/Receiving any data */ UART_Init(UART0,9600); UART_Printf("5digit decimal counter: "); /* Transmit the counter till 9999 */ while(cnt < 9999) { /* Transmit the 4-digit counter value and go to next line */ UART_Printf("\n\r%4u",cnt); /* Increment the counter value after 1-sec */ DELAY_sec(1); cnt++; } while(1); }