Difference between revisions of "UART Programming with Atmega128"

Line 45: Line 45:
 
||RXC0||TXC0||UDRE0||FE0||DOR0||UPE0||U2X0||MPCM0
 
||RXC0||TXC0||UDRE0||FE0||DOR0||UPE0||U2X0||MPCM0
 
|}
 
|}
−
This bit is used to show the status of the received buffer.
+
 
−
* Bit 7 - RXC0 : USART Receive complete
+
This bit is used to show the status of the received buffer.<br>
 +
'''Bit 7 - RXC0 : USART Receive complete'''<br>
 
1 : Unread data in the Receiver buffer<br>
 
1 : Unread data in the Receiver buffer<br>
−
0 : Receive buffer is empty.
+
0 : Receive buffer is empty.<br>
  
−
This bit us used to show the status of the transmitted buffer.
+
This bit us used to show the status of the transmitted buffer.<br>
−
* Bit 6 - TXC0 : USART transmit complete
+
'''Bit 6 - TXC0 : USART transmit complete'''<br>
 
1 : No data present in the buffer register to transmit<br>
 
1 : No data present in the buffer register to transmit<br>
−
0 : Transmit complete interrupt is executed.
+
0 : Transmit complete interrupt is executed.<br>
−
This bit indicates whether Transmit data buffer ready to receive new data.
+
 
−
* Bit 5 - UDRE0 : USART Data Register empty
+
This bit indicates whether Transmit data buffer ready to receive new data.<br>
 +
'''Bit 5 - UDRE0 : USART Data Register empty'''<br>
 
1 : Transmitter buffer is empty <br>
 
1 : Transmitter buffer is empty <br>
−
0 : Transmitter is ready.
+
0 : Transmitter is ready.<br>
  
−
This bit us used to show the Frame error.
+
This bit us used to show the Frame error.<br>
−
* Bit 4 - FE0 : Frame error  
+
'''Bit 4 - FE0 : Frame error''' <br>
 
1 : Next character in the receiver buffer had error <br>
 
1 : Next character in the receiver buffer had error <br>
−
0 : Writing to UCSR0A.
+
0 : Writing to UCSR0A.<br>
  
−
This bit us used to show the Receiver data over run occure.
+
This bit us used to show the Receiver data over run occure.<br>
−
* Bit 3 - DOR0 : Data over run
+
'''Bit 3 - DOR0 : Data over run'''<br>
 
1 : Receiver buffer is full (Receiver data over run occure)<br>
 
1 : Receiver buffer is full (Receiver data over run occure)<br>
−
0 : Writing to UCSR0A.
+
0 : Writing to UCSR0A.<br>
  
−
This bit us used to show the parity error.
+
This bit us used to show the parity error.<br>
−
* Bit 2 - UPE0 : Parity Error
+
'''Bit 2 - UPE0 : Parity Error'''<br>
 
1 : Next character in the receiver buffer had a parity error<br>
 
1 : Next character in the receiver buffer had a parity error<br>
−
0 : Writing to UCSR0A.
+
0 : Writing to UCSR0A.<br>
  
−
This bit has effect for the Asynchronous operation. For Synchronous operation write this bit to 0.
+
This bit has effect for the Asynchronous operation. For Synchronous operation write this bit to 0.<br>
−
* Bit 1 - U2X0: Double the USART transmission speed
+
'''Bit 1 - U2X0: Double the USART transmission speed'''<br>
 
1 :Reduces the  divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate of Asynchronous communication <br>
 
1 :Reduces the  divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate of Asynchronous communication <br>
−
0 : Synchronous operation.
+
0 : Synchronous operation.<br>
  
−
This bit enables the multiprocessor communication.
+
This bit enables the multiprocessor communication.<br>
−
* Bit 1 - MPCM0: Multiprocessor communication mode  
+
'''Bit 0 - MPCM0: Multiprocessor communication mode''' <br>
 
1 :All the incoming frames received by the USART Receiver that do not contain address information will be ignored. <br>
 
1 :All the incoming frames received by the USART Receiver that do not contain address information will be ignored. <br>
 
0 : Writing to UCSR0A.
 
0 : Writing to UCSR0A.
  
  
 +
{| style="text-align:center;" class="table table-condensed table-bordered"
 +
!colspan = '8'|UCSR0B
 +
|+USART0 Control and Status Register B
 +
|D7||D6||D5||D4||D3||D2||D1||D0
 +
|-class="success"
 +
||RXCIE0||TXCIE0||UDREIE0||RXEN0||TXEN0||UCSZ20||RXB80||TXB80
 +
|}
  
 +
This bit is used to show the status of the received interrupt.<br>
 +
'''Bit 7 - RXCIE0: RX Complete Interrupt Enable'''<br>
 +
1 : A USART0 Receive Complete interrupt will be generated<br>
 +
0 : no interrupt.<br>
  
 +
This bit us used to show the status of the transmitted interrupt .<br>
 +
'''Bit 6 - TXC0 : USART transmit complete'''<br>
 +
1 : A USART0 Transmit Complete interrupt will be generated<br>
 +
0 : no interrupt.<br>
  
  
 +
'''Bit 5 - UDRIE0: USART Data Register Empty Interrupt Enable'''<br>
 +
1 : enables interrupt on the UDRE0 flag <br>
 +
0 : no interrupt.<br>
  
  
−
{| style="text-align:center;" class="table table-condensed table-bordered"
+
'''Bit 4 - RXEN0: Receiver Enable''' <br>
−
!colspan = '8'|UCSRB
+
1 : The Receiver will override normal port operation for the RxDn pin <br>
−
|+USART Control and Status Register B
+
0 : Receiver will flush the receive buffer invalidating the FEn, DORn and UPEn flags.<br>
−
|D7||D6||D5||D4||D3||D2||D1||D0
+
−
|-class="success"
+
−
||RXCIE||TXCIE||UDREIE||RXEN||TXEN||UCSZ2||RXB8||TXB8
+
  
−
|}
 
  
−
♦ '''Bit 4 - RXEN: Receiver Enable'''
+
'''Bit 3 - TXEN0: Transmitter Enable'''<br>
 +
1 : The Transmitter will override normal port operation for the TxDn pin<br>
 +
0 : the Transmitter will not become effective until ongoing and pending transmissions are completed<br>
  
−
Writing this bit to one enables the USART Receiver.
 
  
−
♦ '''Bit 3 - TXEN: Transmitter Enable'''
+
'''Bit 2 - UCSZ02: Character Size'''<br>
 +
1 : number of data bits (character size) in a frame the Receiver and Transmitter use<br>
 +
0 :nil <br>
 +
 
 +
 
 +
'''Bit 1 - RXB8n: Receive Data Bit 8'''<br>
 +
RXB8n is the ninth data bit of the received character when operating with serial frames with 9-data bits. Must be read before reading the low bits from UDR0.
 +
 
 +
 
 +
'''Bit 0 - TXB8n: Transmit Data Bit 8''' <br>
 +
TXB8n is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be written before writing the low bits to UDR0.
  
−
Writing this bit to one enables the USART Transmitter.
 
  
 
{| style="text-align:center;" class="table table-condensed table-bordered"  
 
{| style="text-align:center;" class="table table-condensed table-bordered"  
−
!colspan = '8'|UCSRC
+
!colspan = '8'|UCSR0C
−
|+USART Control and Status Register C
+
|+USART0 Control and Status Register C
 
|D7||D6||D5||D4||D3||D2||D1||D0
 
|D7||D6||D5||D4||D3||D2||D1||D0
 
|-class="success"
 
|-class="success"
−
||URSEL||UMSEL||UPM1||UPM0||USBS||UCSZ1||UCSZ0||UCPOL
+
||URSEL0||UMSEL0||UPM10||UPM00||USBS0||UCSZ10||UCSZ00||UCPOL0
 +
|}
  
 +
This bit is used to show the status of the received interrupt.<br>
 +
'''Bit 7 - Reserved Bit'''<br>
 +
 +
This bit selects between Asynchronous and Synchronous mode of operation.<br>
 +
'''Bit 6 - UMSEL0: USART Mode Select'''<br>
 +
1 : Synchronous Operation<br>
 +
0 : Asynchronous Operation.<br>
 +
 +
These bits enable and set type of parity generation and check<br>
 +
'''Bit 5:4 – UPM01:0: Parity Mode'''<br>
 +
{| class="wikitable"
 +
|-
 +
! UPM01 !! UPM00 !! Parity Mode
 +
|-
 +
| 0 || 0 || Disabled
 +
|-
 +
| 0 || 1 || (Reserved)
 +
|-
 +
| 1 || 0 || Enabled,Even parity
 +
|-
 +
| 1 || 1 || Enabled,odd parity
 
|}
 
|}
 +
 +
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting.
 +
'''Bit 3 - USBS0: Stop Bit Select''' <br>
 +
1 : 2-bits<br>
 +
0 : 1-bit<br>
 +
 +
The UCSZ01:0 bits combined with the UCSZ02 bit in UCSR0B sets the number of data bits (character size) in a frame the Receiver and Transmitter use.
 +
'''Bit 2:1 - UCSZ01:0: Character Size'''<br>
 +
{| class="wikitable"
 +
|-
 +
! UCSZ02 !! UCSZ01 !! UCSZ00!! Character Size
 +
|-
 +
| 0 || 0 || 0 || 5-bit
 +
|-
 +
| 0|| 0 || 1 ||  6-bit
 +
|-
 +
| 0 || 1 || 0 ||  7-bit
 +
|-
 +
| 0 || 1|| 1 ||  8-bit
 +
|-
 +
| 1 || 0 || 0 || Reserved
 +
|-
 +
| 1 || 0 || 1 || Reserved
 +
|-
 +
| 1 || 1 || 0 ||  Reserved
 +
|-
 +
| 1 || 1 || 1 || 9-bit
 +
|}
 +
 +
This bit is used for synchronous mode only.
 +
'''Bit 0 - UCPOL0: Clock Polarity'''<br>
 +
1 : Synchronous<br>
 +
0 :Asynchronous<br>
  
  

Revision as of 19:43, 19 April 2016

In this tutorial we are going to learn how to communicate with PC using UART protocol. Atmega128 has two USART, USART0 and USART1. For more information about basics of UART refer AVR tutorial. We will discuss in this tutorial about USART0 thoroughly.

UART Module

Atmega128 has two UART are named USART0 and USART1. Each UART has Receiver and Transmitter pins which are name as RXD0 and TXD0 for USART0 and similarly RXD1 and TXD1 for USART1. Atmega128 has multiplexed pins so we configure these if we want to use UART's. Below table shows the multiplexed pins related to UART.

Port Pin Pin no. Port Function Port Function
PE0 2 PDI RXD0
PE1 3 PDO TXD0
PD2 27 INT2 RXD1
PD3 28 INT3 TXD1

UART Register

The below table shown registers are associated with Atmega128 UART.

Register Description
UDR USART Data Register
UCSR0A USART0 Control and Status Register A
UCSR0B USART0 Control and Status Register B
UCSR0C USART0 Control and Status Register C
UBRR0L USART0 Baud Rate Register L
UBRR0H USART0 Baud Rate Register H

UART Register Configuration

We will see now how to configure the UART registers.

UCSR0A
USART0 Control and Status Register A
D7 D6 D5 D4 D3 D2 D1 D0
RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0

This bit is used to show the status of the received buffer.
Bit 7 - RXC0 : USART Receive complete
1 : Unread data in the Receiver buffer
0 : Receive buffer is empty.

This bit us used to show the status of the transmitted buffer.
Bit 6 - TXC0 : USART transmit complete
1 : No data present in the buffer register to transmit
0 : Transmit complete interrupt is executed.

This bit indicates whether Transmit data buffer ready to receive new data.
Bit 5 - UDRE0 : USART Data Register empty
1 : Transmitter buffer is empty
0 : Transmitter is ready.

This bit us used to show the Frame error.
Bit 4 - FE0 : Frame error
1 : Next character in the receiver buffer had error
0 : Writing to UCSR0A.

This bit us used to show the Receiver data over run occure.
Bit 3 - DOR0 : Data over run
1 : Receiver buffer is full (Receiver data over run occure)
0 : Writing to UCSR0A.

This bit us used to show the parity error.
Bit 2 - UPE0 : Parity Error
1 : Next character in the receiver buffer had a parity error
0 : Writing to UCSR0A.

This bit has effect for the Asynchronous operation. For Synchronous operation write this bit to 0.
Bit 1 - U2X0: Double the USART transmission speed
1 :Reduces the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate of Asynchronous communication
0 : Synchronous operation.

This bit enables the multiprocessor communication.
Bit 0 - MPCM0: Multiprocessor communication mode
1 :All the incoming frames received by the USART Receiver that do not contain address information will be ignored.
0 : Writing to UCSR0A.


UCSR0B
USART0 Control and Status Register B
D7 D6 D5 D4 D3 D2 D1 D0
RXCIE0 TXCIE0 UDREIE0 RXEN0 TXEN0 UCSZ20 RXB80 TXB80

This bit is used to show the status of the received interrupt.
Bit 7 - RXCIE0: RX Complete Interrupt Enable
1 : A USART0 Receive Complete interrupt will be generated
0 : no interrupt.

This bit us used to show the status of the transmitted interrupt .
Bit 6 - TXC0 : USART transmit complete
1 : A USART0 Transmit Complete interrupt will be generated
0 : no interrupt.


Bit 5 - UDRIE0: USART Data Register Empty Interrupt Enable
1 : enables interrupt on the UDRE0 flag
0 : no interrupt.


Bit 4 - RXEN0: Receiver Enable
1 : The Receiver will override normal port operation for the RxDn pin
0 : Receiver will flush the receive buffer invalidating the FEn, DORn and UPEn flags.


Bit 3 - TXEN0: Transmitter Enable
1 : The Transmitter will override normal port operation for the TxDn pin
0 : the Transmitter will not become effective until ongoing and pending transmissions are completed


Bit 2 - UCSZ02: Character Size
1 : number of data bits (character size) in a frame the Receiver and Transmitter use
0 :nil


Bit 1 - RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when operating with serial frames with 9-data bits. Must be read before reading the low bits from UDR0.


Bit 0 - TXB8n: Transmit Data Bit 8
TXB8n is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be written before writing the low bits to UDR0.


UCSR0C
USART0 Control and Status Register C
D7 D6 D5 D4 D3 D2 D1 D0
URSEL0 UMSEL0 UPM10 UPM00 USBS0 UCSZ10 UCSZ00 UCPOL0

This bit is used to show the status of the received interrupt.
Bit 7 - Reserved Bit

This bit selects between Asynchronous and Synchronous mode of operation.
Bit 6 - UMSEL0: USART Mode Select
1 : Synchronous Operation
0 : Asynchronous Operation.

These bits enable and set type of parity generation and check
Bit 5:4 – UPM01:0: Parity Mode

UPM01 UPM00 Parity Mode
0 0 Disabled
0 1 (Reserved)
1 0 Enabled,Even parity
1 1 Enabled,odd parity

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Bit 3 - USBS0: Stop Bit Select
1 : 2-bits
0 : 1-bit

The UCSZ01:0 bits combined with the UCSZ02 bit in UCSR0B sets the number of data bits (character size) in a frame the Receiver and Transmitter use. Bit 2:1 - UCSZ01:0: Character Size

UCSZ02 UCSZ01 UCSZ00 Character Size
0 0 0 5-bit
0 0 1 6-bit
0 1 0 7-bit
0 1 1 8-bit
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 9-bit

This bit is used for synchronous mode only. Bit 0 - UCPOL0: Clock Polarity
1 : Synchronous
0 :Asynchronous


Video Tutorial

For those of you, who would like to watch instead of read we have made a video with all the gyan.


Downloads

Download the complete project folder from the below link: https://github.com/ExploreEmbedded/ATmega32_ExploreUltraAvrDevKit/archive/master.zip


Have a opinion, suggestion , question or feedback about the article let it out here!


Video Tutorial

For those of you, who would like to watch instead of read we have made a video with all the gyan.



Downloads

Download the complete project folder from the below link: https://github.com/ExploreEmbedded/ATMega-128-Break-Out-BoardDVB-12007/archive/master.zip


Have a opinion, suggestion , question or feedback about the article let it out here!

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