Difference between revisions of "LPC1768: External Interrupts"
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=Using ExploreEmbedded Libraries= | =Using ExploreEmbedded Libraries= | ||
| − | In the above tutorial we discussed how to configure and use the LPC1768 external interrupts. | + | In the above tutorial we discussed how to configure and use the LPC1768 external interrupts.<br> |
Now we will see how to use the ExploreEmbededd external interrupt libraries. | Now we will see how to use the ExploreEmbededd external interrupt libraries. | ||
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| + | The below example demonstrates the difference between the edge triggered and level triggered interrupt.<br> | ||
| + | EINT0 is configured as FALLING edge and counter will be incremented whenever there is a high-to-low pulse on EINT0.<br> | ||
| + | EINT1 is configured as ACTIVE low and counter will be inctermented as long as EINT1 is LOW.<br> | ||
| + | EINT1 counter increments fast as the ISR will be executed multiple times. | ||
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<script src="https://gist.github.com/SaheblalBagwan/1ea1ac239d0136661b81015decefc756.js"></script> | <script src="https://gist.github.com/SaheblalBagwan/1ea1ac239d0136661b81015decefc756.js"></script> | ||
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Revision as of 20:51, 13 April 2016
Contents
Objective:
In this tutorial we will discuss how to configure and use the LPC1768 external interrupts(EINT0-EINT3).
At the end of tutorial we will see how to use the exploreembedded external interrupt library.
EINTx Pins
LPC1768 has four external interrupts EINT0-EINT3.
As LPC1768 pins are multi functional, these four interrupts are available on multiple pins.
Below table shows mapping of EINTx pins.
| Port Pin | PINSEL_FUNC_0 | PINSEL_FUNC_1 | PINSEL_FUNC_2 | PINSEL_FUNC_3 |
|---|---|---|---|---|
| P2.10 | GPIO | EINT0 | NMI | |
| P2.11 | GPIO | EINT1 | I2STX_CLK | |
| P2_12 | GPIO | EINT2 | I2STX_WS | |
| P2.13 | GPIO | EINT3 | I2STX_SDA |
EINT Registers
Below table shows the registers associated with LPC1768 external interrupts.
| Register | Description |
|---|---|
| PINSELx | To configure the pins as External Interrupts |
| EXTINT | External Interrupt Flag Register contains interrupt flags for EINT0,EINT1, EINT2 & EINT3. |
| EXTMODE | External Interrupt Mode register(Level/Edge Triggered) |
| EXTPOLAR | External Interrupt Polarity(Falling/Rising Edge, Active Low/High) |
| EXTINT | ||||
| 31:4 | 3 | 2 | 1 | 0 |
| RESERVED | EINT3 | EINT2 | EINT1 | EINT0 |
EINTx: Bits will be set whenever the interrupt is detected on the particular interrupt pin.
If the interrupts are enabled then the control goes to ISR.
Writing one to specific bit will clear the corresponding interrupt.
| EXTMODE | ||||
| 31:4 | 3 | 2 | 1 | 0 |
| RESERVED | EXTMODE3 | EXTMODE2 | EXTMODE1 | EXTMODE0 |
EXTMODEx: This bits is used to select whether the EINTx pin is level or edge Triggered
0: EINTx is Level Triggered.
1: EINTx is Edge Triggered.
| EXTPOLAR | ||||
| 31:4 | 3 | 2 | 1 | 0 |
| RESERVED | EXTPOLAR3 | EXTPOLAR2 | EXTPOLAR1 | EXTPOLAR0 |
EXTPOLARx: This bits is used to select polarity(LOW/HIGH, FALLING/RISING) of the EINTx interrupt depending on the EXTMODE register.
0: EINTx is Active Low or Falling Edge (depending on EXTMODEx).
1: EINTx is Active High or Rising Edge (depending on EXTMODEx).
Steps to Configure Interrupts
- Configure the pins as external interrupts in PINSELx register.
- Clear any pending interrupts in EXTINT.
- Configure the EINTx as Edge/Level triggered in EXTMODE register.
- Select the polarity(Falling/Rising Edge, Active Low/High) of the interrupt in EXTPOLAR register.
- Finally enable the interrputs by calling NVIC_EnableIRQ() with IRQ number.
Code
Below example shows the toggling of Leds depending on the external interrupts.
Using ExploreEmbedded Libraries
In the above tutorial we discussed how to configure and use the LPC1768 external interrupts.
Now we will see how to use the ExploreEmbededd external interrupt libraries.
The below example demonstrates the difference between the edge triggered and level triggered interrupt.
EINT0 is configured as FALLING edge and counter will be incremented whenever there is a high-to-low pulse on EINT0.
EINT1 is configured as ACTIVE low and counter will be inctermented as long as EINT1 is LOW.
EINT1 counter increments fast as the ISR will be executed multiple times.