Difference between revisions of "LPC1768: SPI Programming"

m
m
Line 34: Line 34:
  
 
=SPI Register Configuration=
 
=SPI Register Configuration=
−
=====FCR ( FIFO Control Register )=====
+
=====SPCR ( SPI Control Register )=====
  
 
{| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
 
{| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
−
!colspan = '9'|FCR
+
!colspan = '9'|SPCR
 +
|-
 +
|31:12 || 11:8|| 7 || 6 ||  5 || 4  || 3 || 2 ||1: 0 
 +
|-
 +
| RESERVED || BITS|| SPIE||  LSBF  || MSTR || CPOL  || CPHA || BIT ENABLE || RESERVED
 +
|}
 +
 
 +
'''Bit 1:0 – RESERVED'''<br>
 +
   
 +
'''Bit 2 – BIT ENABLE:'''<br>
 +
This is used to clear the 16-byte Rx FIFO.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 3 – CPHA:'''<br>
 +
.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 4 – CPOL:'''<br>
 +
This is used for controlling clock polarity.<br>
 +
0 -- SCK is active high.<br>
 +
1 -- SCK is active low.<br>
 +
 +
'''Bit 5 – MSTR:'''<br>
 +
This bit is used for Master mode select.
 +
0 -- Slave Mode.<br>
 +
1 -- Master Mode.<br>
 +
 
 +
'''Bit 6 – LSBF:'''<br>
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 4 – SPIE:'''<br>
 +
This bit is used to enable SPI interrupt.
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 11:8 – BITS:'''<br>
 +
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:<br>
 +
1000 -- 8 Bits per transfer<br>
 +
1001 -- 9 Bits per transfer<br>
 +
1010 -- 10 Bits per transfer<br>
 +
1011 -- 11 Bits per transfer<br>
 +
1100 -- 12 Bits per transfer<br>
 +
1101 -- 13 Bits per transfer<br>
 +
1110 -- 14 Bits per transfer<br>
 +
1111 -- 15 Bits per transfer<br>
 +
0000 -- 16 Bits per transfer<br>
 +
 
 +
'''Bit 31:12 – RESERVED'''<br>
 +
 
 +
 
 +
 
 +
=====SPSR ( SPI Status Register )=====
 +
 
 +
{| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
 +
!colspan = '9'|SPSR
 +
|-
 +
|31:12 || 11:8|| 7 || 6 ||  5 || 4  || 3 || 2 ||1: 0 
 +
|-
 +
| RESERVED || BITS|| SPIE||  LSBF  || MSTR || CPOL  || CPHA || BIT ENABLE || RESERVED
 +
|}
 +
 
 +
'''Bit 1:0 – RESERVED'''<br>
 +
   
 +
'''Bit 2 – BIT ENABLE:'''<br>
 +
This is used to clear the 16-byte Rx FIFO.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 3 – CPHA:'''<br>
 +
.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 4 – CPOL:'''<br>
 +
This is used for controlling clock polarity.<br>
 +
0 -- SCK is active high.<br>
 +
1 -- SCK is active low.<br>
 +
 +
'''Bit 5 – MSTR:'''<br>
 +
This bit is used for Master mode select.
 +
0 -- Slave Mode.<br>
 +
1 -- Master Mode.<br>
 +
 
 +
'''Bit 6 – LSBF:'''<br>
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 4 – SPIE:'''<br>
 +
This bit is used to enable SPI interrupt.
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 11:8 – BITS:'''<br>
 +
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:<br>
 +
1000 -- 8 Bits per transfer<br>
 +
1001 -- 9 Bits per transfer<br>
 +
1010 -- 10 Bits per transfer<br>
 +
1011 -- 11 Bits per transfer<br>
 +
1100 -- 12 Bits per transfer<br>
 +
1101 -- 13 Bits per transfer<br>
 +
1110 -- 14 Bits per transfer<br>
 +
1111 -- 15 Bits per transfer<br>
 +
0000 -- 16 Bits per transfer<br>
 +
 
 +
'''Bit 31:12 – RESERVED'''<br>
 +
 
 +
=====SPDR ( SPI Data Register )=====
 +
 
 +
{| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
 +
!colspan = '9'|SPDR
 +
|-
 +
|31:12 || 11:8|| 7 || 6 ||  5 || 4  || 3 || 2 ||1: 0 
 +
|-
 +
| RESERVED || BITS|| SPIE||  LSBF  || MSTR || CPOL  || CPHA || BIT ENABLE || RESERVED
 +
|}
 +
 
 +
'''Bit 1:0 – RESERVED'''<br>
 +
   
 +
'''Bit 2 – BIT ENABLE:'''<br>
 +
This is used to clear the 16-byte Rx FIFO.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 3 – CPHA:'''<br>
 +
.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 4 – CPOL:'''<br>
 +
This is used for controlling clock polarity.<br>
 +
0 -- SCK is active high.<br>
 +
1 -- SCK is active low.<br>
 +
 +
'''Bit 5 – MSTR:'''<br>
 +
This bit is used for Master mode select.
 +
0 -- Slave Mode.<br>
 +
1 -- Master Mode.<br>
 +
 
 +
'''Bit 6 – LSBF:'''<br>
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 4 – SPIE:'''<br>
 +
This bit is used to enable SPI interrupt.
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 11:8 – BITS:'''<br>
 +
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:<br>
 +
1000 -- 8 Bits per transfer<br>
 +
1001 -- 9 Bits per transfer<br>
 +
1010 -- 10 Bits per transfer<br>
 +
1011 -- 11 Bits per transfer<br>
 +
1100 -- 12 Bits per transfer<br>
 +
1101 -- 13 Bits per transfer<br>
 +
1110 -- 14 Bits per transfer<br>
 +
1111 -- 15 Bits per transfer<br>
 +
0000 -- 16 Bits per transfer<br>
 +
 
 +
'''Bit 31:12 – RESERVED'''<br>
 +
 
 +
=SPI Register Configuration=
 +
=====SPCR ( SPI Control Register )=====
 +
 
 +
{| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
 +
!colspan = '9'|SPCR
 +
|-
 +
|31:12 || 11:8|| 7 || 6 ||  5 || 4  || 3 || 2 ||1: 0 
 +
|-
 +
| RESERVED || BITS|| SPIE||  LSBF  || MSTR || CPOL  || CPHA || BIT ENABLE || RESERVED
 +
|}
 +
 
 +
'''Bit 1:0 – RESERVED'''<br>
 +
   
 +
'''Bit 2 – BIT ENABLE:'''<br>
 +
This is used to clear the 16-byte Rx FIFO.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 3 – CPHA:'''<br>
 +
.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 4 – CPOL:'''<br>
 +
This is used for controlling clock polarity.<br>
 +
0 -- SCK is active high.<br>
 +
1 -- SCK is active low.<br>
 +
 +
'''Bit 5 – MSTR:'''<br>
 +
This bit is used for Master mode select.
 +
0 -- Slave Mode.<br>
 +
1 -- Master Mode.<br>
 +
 
 +
'''Bit 6 – LSBF:'''<br>
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 4 – SPIE:'''<br>
 +
This bit is used to enable SPI interrupt.
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 11:8 – BITS:'''<br>
 +
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:<br>
 +
1000 -- 8 Bits per transfer<br>
 +
1001 -- 9 Bits per transfer<br>
 +
1010 -- 10 Bits per transfer<br>
 +
1011 -- 11 Bits per transfer<br>
 +
1100 -- 12 Bits per transfer<br>
 +
1101 -- 13 Bits per transfer<br>
 +
1110 -- 14 Bits per transfer<br>
 +
1111 -- 15 Bits per transfer<br>
 +
0000 -- 16 Bits per transfer<br>
 +
 
 +
'''Bit 31:12 – RESERVED'''<br>
 +
=SPI Register Configuration=
 +
=====SPCR ( SPI Control Register )=====
 +
 
 +
{| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
 +
!colspan = '9'|SPCR
 +
|-
 +
|31:12 || 11:8|| 7 || 6 ||  5 || 4  || 3 || 2 ||1: 0 
 +
|-
 +
| RESERVED || BITS|| SPIE||  LSBF  || MSTR || CPOL  || CPHA || BIT ENABLE || RESERVED
 +
|}
 +
 
 +
'''Bit 1:0 – RESERVED'''<br>
 +
   
 +
'''Bit 2 – BIT ENABLE:'''<br>
 +
This is used to clear the 16-byte Rx FIFO.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 3 – CPHA:'''<br>
 +
.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 4 – CPOL:'''<br>
 +
This is used for controlling clock polarity.<br>
 +
0 -- SCK is active high.<br>
 +
1 -- SCK is active low.<br>
 +
 +
'''Bit 5 – MSTR:'''<br>
 +
This bit is used for Master mode select.
 +
0 -- Slave Mode.<br>
 +
1 -- Master Mode.<br>
 +
 
 +
'''Bit 6 – LSBF:'''<br>
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 4 – SPIE:'''<br>
 +
This bit is used to enable SPI interrupt.
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 11:8 – BITS:'''<br>
 +
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:<br>
 +
1000 -- 8 Bits per transfer<br>
 +
1001 -- 9 Bits per transfer<br>
 +
1010 -- 10 Bits per transfer<br>
 +
1011 -- 11 Bits per transfer<br>
 +
1100 -- 12 Bits per transfer<br>
 +
1101 -- 13 Bits per transfer<br>
 +
1110 -- 14 Bits per transfer<br>
 +
1111 -- 15 Bits per transfer<br>
 +
0000 -- 16 Bits per transfer<br>
 +
 
 +
'''Bit 31:12 – RESERVED'''<br>
 +
 
 +
 
 +
=====SPCR ( SPI Control Register )=====
 +
 
 +
{| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
 +
!colspan = '9'|SPCR
 +
|-
 +
|31:12 || 11:8|| 7 || 6 ||  5 || 4  || 3 || 2 ||1: 0 
 +
|-
 +
| RESERVED || BITS|| SPIE||  LSBF  || MSTR || CPOL  || CPHA || BIT ENABLE || RESERVED
 +
|}
 +
 
 +
'''Bit 1:0 – RESERVED'''<br>
 +
   
 +
'''Bit 2 – BIT ENABLE:'''<br>
 +
This is used to clear the 16-byte Rx FIFO.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 3 – CPHA:'''<br>
 +
.<br>
 +
0-- .<br>
 +
1-- .<br>
 +
 
 +
'''Bit 4 – CPOL:'''<br>
 +
This is used for controlling clock polarity.<br>
 +
0 -- SCK is active high.<br>
 +
1 -- SCK is active low.<br>
 +
 +
'''Bit 5 – MSTR:'''<br>
 +
This bit is used for Master mode select.
 +
0 -- Slave Mode.<br>
 +
1 -- Master Mode.<br>
 +
 
 +
'''Bit 6 – LSBF:'''<br>
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 4 – SPIE:'''<br>
 +
This bit is used to enable SPI interrupt.
 +
0 -- .<br>
 +
1 -- .<br>
 +
 +
'''Bit 11:8 – BITS:'''<br>
 +
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:<br>
 +
1000 -- 8 Bits per transfer<br>
 +
1001 -- 9 Bits per transfer<br>
 +
1010 -- 10 Bits per transfer<br>
 +
1011 -- 11 Bits per transfer<br>
 +
1100 -- 12 Bits per transfer<br>
 +
1101 -- 13 Bits per transfer<br>
 +
1110 -- 14 Bits per transfer<br>
 +
1111 -- 15 Bits per transfer<br>
 +
0000 -- 16 Bits per transfer<br>
 +
 
 +
'''Bit 31:12 – RESERVED'''<br>
 +
 
 +
 
 +
 
 +
=====SPCCR ( SPI Clock Counter Register )=====
 +
 
 +
{| class="wikitable" style="text-align:center; background-color:#ABCDEF;margin: 1em auto 1em auto"
 +
!colspan = '9'|SPCCR
 
|-
 
|-
 
|31:12 || 11:8|| 7 || 6 ||  5 || 4  || 3 || 2 ||1: 0   
 
|31:12 || 11:8|| 7 || 6 ||  5 || 4  || 3 || 2 ||1: 0   

Revision as of 11:44, 17 June 2015

Objective

LPC1768 SPI Block

The below block diagram shows the SPI input pins multiplexed with other GPIO pins.
The SPI pin can be enabled by configuring the corresponding PINSEL register to select SPI function.
When the SPI function is selected for that pin in the Pin Select register, other Digital signals are disconnected from the SPI input pins.

Port Pin Pin Number PINSEL_FUNC_0 PINSEL_FUNC_1 PINSEL_FUNC_2 PINSEL_FUNC_3
P0.15 47 GPIO TXD1 SCK0 SCK
P0.16 48 GPIO RXD1 SSEL0 SSEL
P0.17 46 GPIO CTS1 MISO0 MISO
P0.18 45 GPIO DCD1 MOSI0 MOSI

SPI Registers

Register Description
SPCR SPI Control Register : used to configure SPI
SPSR SPI status Register :
SPDR SPI Data Register : contains received data or data to be transmitted
SPCCR SPI Clock Counter Register : used to control master SCK frequency



SPI Register Configuration

SPCR ( SPI Control Register )
SPCR
31:12 11:8 7 6 5 4 3 2 1: 0
RESERVED BITS SPIE LSBF MSTR CPOL CPHA BIT ENABLE RESERVED

Bit 1:0 – RESERVED

Bit 2 – BIT ENABLE:
This is used to clear the 16-byte Rx FIFO.
0-- .
1-- .

Bit 3 – CPHA:
.
0-- .
1-- .

Bit 4 – CPOL:
This is used for controlling clock polarity.
0 -- SCK is active high.
1 -- SCK is active low.

Bit 5 – MSTR:
This bit is used for Master mode select. 0 -- Slave Mode.
1 -- Master Mode.

Bit 6 – LSBF:
0 -- .
1 -- .

Bit 4 – SPIE:

This bit is used to enable SPI interrupt. 0 -- .
1 -- .

Bit 11:8 – BITS:
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:
1000 -- 8 Bits per transfer
1001 -- 9 Bits per transfer
1010 -- 10 Bits per transfer
1011 -- 11 Bits per transfer
1100 -- 12 Bits per transfer
1101 -- 13 Bits per transfer
1110 -- 14 Bits per transfer
1111 -- 15 Bits per transfer
0000 -- 16 Bits per transfer

Bit 31:12 – RESERVED


SPSR ( SPI Status Register )
SPSR
31:12 11:8 7 6 5 4 3 2 1: 0
RESERVED BITS SPIE LSBF MSTR CPOL CPHA BIT ENABLE RESERVED

Bit 1:0 – RESERVED

Bit 2 – BIT ENABLE:
This is used to clear the 16-byte Rx FIFO.
0-- .
1-- .

Bit 3 – CPHA:
.
0-- .
1-- .

Bit 4 – CPOL:
This is used for controlling clock polarity.
0 -- SCK is active high.
1 -- SCK is active low.

Bit 5 – MSTR:
This bit is used for Master mode select. 0 -- Slave Mode.
1 -- Master Mode.

Bit 6 – LSBF:
0 -- .
1 -- .

Bit 4 – SPIE:

This bit is used to enable SPI interrupt. 0 -- .
1 -- .

Bit 11:8 – BITS:
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:
1000 -- 8 Bits per transfer
1001 -- 9 Bits per transfer
1010 -- 10 Bits per transfer
1011 -- 11 Bits per transfer
1100 -- 12 Bits per transfer
1101 -- 13 Bits per transfer
1110 -- 14 Bits per transfer
1111 -- 15 Bits per transfer
0000 -- 16 Bits per transfer

Bit 31:12 – RESERVED

SPDR ( SPI Data Register )
SPDR
31:12 11:8 7 6 5 4 3 2 1: 0
RESERVED BITS SPIE LSBF MSTR CPOL CPHA BIT ENABLE RESERVED

Bit 1:0 – RESERVED

Bit 2 – BIT ENABLE:
This is used to clear the 16-byte Rx FIFO.
0-- .
1-- .

Bit 3 – CPHA:
.
0-- .
1-- .

Bit 4 – CPOL:
This is used for controlling clock polarity.
0 -- SCK is active high.
1 -- SCK is active low.

Bit 5 – MSTR:
This bit is used for Master mode select. 0 -- Slave Mode.
1 -- Master Mode.

Bit 6 – LSBF:
0 -- .
1 -- .

Bit 4 – SPIE:

This bit is used to enable SPI interrupt. 0 -- .
1 -- .

Bit 11:8 – BITS:
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:
1000 -- 8 Bits per transfer
1001 -- 9 Bits per transfer
1010 -- 10 Bits per transfer
1011 -- 11 Bits per transfer
1100 -- 12 Bits per transfer
1101 -- 13 Bits per transfer
1110 -- 14 Bits per transfer
1111 -- 15 Bits per transfer
0000 -- 16 Bits per transfer

Bit 31:12 – RESERVED

SPI Register Configuration

SPCR ( SPI Control Register )
SPCR
31:12 11:8 7 6 5 4 3 2 1: 0
RESERVED BITS SPIE LSBF MSTR CPOL CPHA BIT ENABLE RESERVED

Bit 1:0 – RESERVED

Bit 2 – BIT ENABLE:
This is used to clear the 16-byte Rx FIFO.
0-- .
1-- .

Bit 3 – CPHA:
.
0-- .
1-- .

Bit 4 – CPOL:
This is used for controlling clock polarity.
0 -- SCK is active high.
1 -- SCK is active low.

Bit 5 – MSTR:
This bit is used for Master mode select. 0 -- Slave Mode.
1 -- Master Mode.

Bit 6 – LSBF:
0 -- .
1 -- .

Bit 4 – SPIE:

This bit is used to enable SPI interrupt. 0 -- .
1 -- .

Bit 11:8 – BITS:
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:
1000 -- 8 Bits per transfer
1001 -- 9 Bits per transfer
1010 -- 10 Bits per transfer
1011 -- 11 Bits per transfer
1100 -- 12 Bits per transfer
1101 -- 13 Bits per transfer
1110 -- 14 Bits per transfer
1111 -- 15 Bits per transfer
0000 -- 16 Bits per transfer

Bit 31:12 – RESERVED

SPI Register Configuration

SPCR ( SPI Control Register )
SPCR
31:12 11:8 7 6 5 4 3 2 1: 0
RESERVED BITS SPIE LSBF MSTR CPOL CPHA BIT ENABLE RESERVED

Bit 1:0 – RESERVED

Bit 2 – BIT ENABLE:
This is used to clear the 16-byte Rx FIFO.
0-- .
1-- .

Bit 3 – CPHA:
.
0-- .
1-- .

Bit 4 – CPOL:
This is used for controlling clock polarity.
0 -- SCK is active high.
1 -- SCK is active low.

Bit 5 – MSTR:
This bit is used for Master mode select. 0 -- Slave Mode.
1 -- Master Mode.

Bit 6 – LSBF:
0 -- .
1 -- .

Bit 4 – SPIE:

This bit is used to enable SPI interrupt. 0 -- .
1 -- .

Bit 11:8 – BITS:
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:
1000 -- 8 Bits per transfer
1001 -- 9 Bits per transfer
1010 -- 10 Bits per transfer
1011 -- 11 Bits per transfer
1100 -- 12 Bits per transfer
1101 -- 13 Bits per transfer
1110 -- 14 Bits per transfer
1111 -- 15 Bits per transfer
0000 -- 16 Bits per transfer

Bit 31:12 – RESERVED


SPCR ( SPI Control Register )
SPCR
31:12 11:8 7 6 5 4 3 2 1: 0
RESERVED BITS SPIE LSBF MSTR CPOL CPHA BIT ENABLE RESERVED

Bit 1:0 – RESERVED

Bit 2 – BIT ENABLE:
This is used to clear the 16-byte Rx FIFO.
0-- .
1-- .

Bit 3 – CPHA:
.
0-- .
1-- .

Bit 4 – CPOL:
This is used for controlling clock polarity.
0 -- SCK is active high.
1 -- SCK is active low.

Bit 5 – MSTR:
This bit is used for Master mode select. 0 -- Slave Mode.
1 -- Master Mode.

Bit 6 – LSBF:
0 -- .
1 -- .

Bit 4 – SPIE:

This bit is used to enable SPI interrupt. 0 -- .
1 -- .

Bit 11:8 – BITS:
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:
1000 -- 8 Bits per transfer
1001 -- 9 Bits per transfer
1010 -- 10 Bits per transfer
1011 -- 11 Bits per transfer
1100 -- 12 Bits per transfer
1101 -- 13 Bits per transfer
1110 -- 14 Bits per transfer
1111 -- 15 Bits per transfer
0000 -- 16 Bits per transfer

Bit 31:12 – RESERVED


SPCCR ( SPI Clock Counter Register )
SPCCR
31:12 11:8 7 6 5 4 3 2 1: 0
RESERVED BITS SPIE LSBF MSTR CPOL CPHA BIT ENABLE RESERVED

Bit 1:0 – RESERVED

Bit 2 – BIT ENABLE:
This is used to clear the 16-byte Rx FIFO.
0-- .
1-- .

Bit 3 – CPHA:
.
0-- .
1-- .

Bit 4 – CPOL:
This is used for controlling clock polarity.
0 -- SCK is active high.
1 -- SCK is active low.

Bit 5 – MSTR:
This bit is used for Master mode select. 0 -- Slave Mode.
1 -- Master Mode.

Bit 6 – LSBF:
0 -- .
1 -- .

Bit 4 – SPIE:

This bit is used to enable SPI interrupt. 0 -- .
1 -- .

Bit 11:8 – BITS:
When bit 2 ( BIT ENABLE ) of this register is 1, this field controls the number of bits per transfer:
1000 -- 8 Bits per transfer
1001 -- 9 Bits per transfer
1010 -- 10 Bits per transfer
1011 -- 11 Bits per transfer
1100 -- 12 Bits per transfer
1101 -- 13 Bits per transfer
1110 -- 14 Bits per transfer
1111 -- 15 Bits per transfer
0000 -- 16 Bits per transfer

Bit 31:12 – RESERVED

Steps for using SPI

Initialize SPI

Send Data

Receive Data

Code

Example 1

Using Explore Embedded Libraries

Retrieved from "https://exploreembedded.com/wiki/index.php?title=LPC1768:_SPI_Programming&oldid=6066"